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complete, dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output dacs preliminary technical data ad5722r/ad5732r/AD5752R rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features complete, dual, 12-/14-/16-bit d/a converter operates from single/dual supplies software programmable output range +5 v, +10 v, +10.8 v, 5 v, 10 v, 10.8 v inl error: 16 lsb maximum, dnl error: 1 lsb maximum total unadjusted error (tue): 0.1% fsr maximum settling time: 10 s maximum integrated reference: 5 ppm/c typ. integrated reference buffers output control during power-up/brownout simultaneous updating via ldac asynchronous clr to zero-/mid-scale dsp-/microcontroller-compatible serial interface 24-lead tssop operating temperature range: ?40c to +85c i cmos? process technology 1 applications industrial automation closed-loop servo control, process control automotive test and measurement programmable logic controllers general description the ad5722r/ad5732r/AD5752R are dual, 12-/14-/16-bit, serial input, voltage output, digital-to-analog converters. they operate from single supply voltages of +4.5 v up to +16.5 v or dual supply voltages from 4.5 v up to 16.5 v. nominal full- scale output range is software-selectable from the options of +5 v, +10 v, +10.8 v, 5 v, 10 v, or 10.8 v. integrated output amplifiers, reference buffers, and proprietary power-up/power- down control circuitry are also provided. the parts offer guaranteed monotonicity, integral nonlinearity (inl) of 16 lsb maximum, low noise, 10 s maximum settling time, and an on-chip +2.5 v reference. the ad5722r/ad5732r/AD5752R use a serial interface that operates at clock rates up to 30 mhz and are compatible with dsp and microcontroller interface standards. double buffering allows the simultaneous updating of all dacs. the input coding is user-selectable twos complement or offset binary for a bipolar output (depending on the state of pin bin/ 2scomp ), and straight binary for a unipolar output. the asynchronous clear function clears all dac registers to a user-selectable zero-scale or mid-scale output. the parts are available in a 24-lead tssop and offer guaranteed specifications over the ?40c to +85c industrial temperature range. table 1. pin compatible devices part number description ad5722/ad5732/ad5752 ad5722r/ad5732r/AD5752R without internal reference. ad5724/ad5734/ad5754 complete, quad, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output dac. ad5724r/ad5734r/ad5754r ad5724/ad5734/ad5754 with internal reference. 1 for analog systems designers within industrial/instrumentation equipment oems who need high performance ics at higher-voltage levels, icmos is a technology platform that enables the development of analog ics capable of 30 v and operating at 15 v supplies while allowing dramatic red uctions in power consumption and package size, and increase d ac and dc performance.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 3 dual supply specifications .............................................................. 4 single supply specifications ............................................................ 6 ac performance characteristics ................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings.......................................................... 11 esd caution................................................................................ 11 pin configuration and function descriptions........................... 12 typical performance characteristics ........................................... 13 terminology .................................................................................... 19 theory of operation ...................................................................... 21 architecture................................................................................. 21 serial interface ............................................................................ 21 load dac ( ldac )..................................................................... 23 asynchronous clear ( clr )....................................................... 23 configuring the ad5722r/ad5732r/AD5752R .................. 23 transfer function....................................................................... 23 input register.............................................................................. 27 data register............................................................................... 27 output range select register ................................................... 28 control register ......................................................................... 28 power control register ............................................................. 29 features ............................................................................................ 30 analog output control ............................................................. 30 overcurrent protection ............................................................. 30 thermal shutdown .................................................................... 30 internal reference ...................................................................... 30 applications information .............................................................. 31 layout guidelines....................................................................... 31 galvanically isolated interface ................................................. 31 microprocessor interfacing....................................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history prc C preliminary revision, november 16, 2007
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 3 of 32 functional block diagram dac b input register a input register b 16 16 dac a ldac refin/refout v out b v out a reference buffers sdin sclk sync sdo dv cc 2.5v reference gnd 16 dac_gnd (2) sig_gnd (2) ad5722r/ad5732r/AD5752R input shift register an d control logic a v dd av ss dac register a dac register b clr bin/2scomp 0 6466-001 figure 1.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 4 of 32 specifications dual supply specifications av dd = 4.5 v 1 to 16.5 v, av ss = ?4.5 v 1 to ?16.5 v, gnd = 0 v, refin= 2.5 v external, dv cc = 2.7 v to 5.5 v r load = 2 k?, c load = 200 pf; all specifications t min to t max , 10 v range unless otherwise noted. table 2. parameter value unit test conditions/comments accuracy outputs unloaded bipolar output resolution AD5752R 16 bits ad5732r 14 bits ad5722r 12 bits total unadjusted error (tue) 0.1 % fsr ma x over temperature, supplies, and time relative accuracy (inl) b grade 16 lsb max @ 16-bit resolution differential nonlinearity (dnl) 1 lsb max guaranteed monotonic (@ 16-bit resolution) bipolar zero error 5 mv max @ 25c, error at other temperatures obtained using bipolar zero tc bipolar zero tc 2 8 ppm fsr/c max zero-scale error 1 mv max @ 25c, error at other temperatures obtained using zero-scale tc zero-scale tc 2 8 ppm fsr/c max gain error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 8 ppm fsr/c max dc crosstalk 2 0.6 lsb max @ 16-bit resolution unipolar output av ss = 0 v resolution AD5752R 16 bits ad5732r 14 bits ad5722r 12 bits total unadjusted error (tue) 0.1 % fsr ma x over temperature, supplies, and time relative accuracy (inl) b grade 16 lsb max @ 16-bit resolution differential nonlinearity (dnl) 1 lsb max guaranteed monotonic (@ 16 bit-resolution) zero-scale error +10 mv max @ 25c, error at other temperatures obtained using zero-scale tc zero-scale tc 2 4 ppm fsr/c max offset error 10 mv max gain error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 4 ppm fsr/c max dc crosstalk 2 0.6 lsb max @ 16-bit resolution reference input/output reference input 2 reference input voltage 2.5 v nom 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 2 to 3 v min to v max reference output output voltage 2.498 to 2.502 v min to v max @ 25c reference tc 5 ppm/c typ 10 ppm/c max output noise (0.1 hz to 10 hz) 2 18 v p-p typ noise spectral density 2 75 nv/hz typ @ 10 khz output voltage drift vs. time 2 40 ppm/500 hr typ 50 ppm/1000 hr typ
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 5 of 32 parameter value unit test conditions/comments output characteristics 2 output voltage range 10.8 v min to v max av dd /av ss = 11.7 v min , refin = +2.5 v 12 v min to v max av dd /av ss = 12.9 v min, refin = +3 v headroom 0.9 v max 0.5 v typ output voltage tc 8 ppm fsr/c max output voltage drift vs. time 12 ppm fsr/500 hr typ 15 ppm fsr/1000 hr typ short-circuit current 20 ma max load 2 k? min for specified performance capacitive load stability 4000 pf max dc output impedance 0.5 ? typ digital inputs 2 dv cc = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 1 a max per pin pin capacitance 10 pf typ per pin digital outputs (sdo) 2 v ol , output low voltage 0.4 v max dv cc = 5 v 10%, sinking 200 a v oh , output high voltage dv cc ? 1 v min dv cc = 5 v 10%, sourcing 200 a v ol , output low voltage 0.4 v max dv cc = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dv cc ? 0.5 v min dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max high impedance output capacitance 5 pf typ power requirements av dd 4.5 to 16.5 v min to v max av ss -4.5 to -16.5 v min to v max dv cc 2.7 to 5.5 v min to v max power supply sensitivity 2 ?v out /?v dd ?75 db typ ai dd 2 ma/channel max outputs unloaded ai ss 1.5 ma/channel max outputs unloaded di cc 1 a max v ih = dv cc , v il = gnd, 0.5 a typ power dissipation tbd mw typ 12 v operation, outputs unloaded power-down currents ai dd tbd a typ ai ss tbd a typ di cc tbd a typ 1 for specified perfor mance minimum headroom requirement is 0.9v 2 guaranteed by characterization. not production tested.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 6 of 32 single supply specifications av dd = 4.5 v 1 to 16.5 v, av ss = 0 v, gnd = 0 v, refin= 2.5 v external, dv cc = 2.7 v to 5.5 v r load = 2 k?, c load = 200 pf; all specifications t min to t max , 10 v range unless otherwise noted. table 3. parameter value unit test conditions/comments accuracy outputs unloaded resolution AD5752R 16 bits ad5732r 14 bits ad5722r 12 bits total unadjusted error (tue) 0.1 % fsr max across temperature and supplies relative accuracy (inl) b grade 16 lsb max @ 16-bit resolution differential nonlinearity (dnl) 1 lsb max guaranteed monotonic (@ 16-bit resolution) zero-scale error +10 mv max @ 25c, error at other temperatures obtained using zero-scale tc zero-scale tc 2 4 ppm fsr/c max offset error 10 mv max gain error 0.02 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 8 ppm fsr/c max dc crosstalk 2 0.6 lsb max @ 16-bit resolution reference input/output reference input 2 reference input voltage 2.5 v nom 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 2 to 3 v min to v max reference output output voltage 2.498 to 2.502 v min to v max @ 25c reference tc 5 ppm/c max output noise (0.1 hz to 10 hz) 2 18 v p-p typ noise spectral density 2 75 nv/hz typ @ 10 khz output drift vs. time 2 40 ppm/500 hr typ 50 ppm/1000 hr typ output characteristics 2 output voltage range 10.8 v max av dd = 11.7 v min, refin = 2.5 v 12 v max av dd = 12.9 v min, refin = 3.75 v headroom 0.9 v max 0.5 v typ output voltage tc 8 ppm fsr/c max output voltage drift vs. time 12 ppm/500 hr typ 15 ppm/1000 hr typ short circuit current 20 ma typ load 2 k? max for specified performance capacitive load stability 4000 pf max dc output impedance 0.5 ? typ digital inputs 2 dv cc = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 1 a max per pin pin capacitance 5 pf max per pin digital outputs (sdo) 2 v ol , output low voltage 0.4 v max dv cc = 5 v 10%, sinking 200 a v oh , output high voltage dv cc ? 1 v min dv cc = 5 v 10%, sourcing 200 a
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 7 of 32 parameter value unit test conditions/comments v ol , output low voltage 0.4 v max dv cc = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dv cc ? 0.5 v min dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max high impedance output capacitance 5 pf typ power requirements av dd 4.5 to 16.5 v min to v max dv cc 2.7 to 5.5 v min to v max power supply sensitivity 2 ?v out /?v dd ?75 db typ ai dd 2.75 ma/channel max outputs unloaded di cc 1 a max v ih = dv cc , v il = gnd, 0.5 a typ power dissipation tbd mw typ 12 v operation, outputs unloaded 1 for specified perfor mance minimum headroom requirement is 0.9v 2 guaranteed by characterization. not production tested. ac performance characteristics av dd = 4.5 v 1 to 16.5 v, av ss = ?4.5 v to ?16.5 v / 0v, gnd = 0 v, refin= 2.5 v external, dv cc = 2.7 v to 5.5 v r load = 2 k?, c load = 200 pf; all specifications t min to t max , 10 v range unless otherwise noted. table 4. parameter 2 b grade unit test conditions/comments dynamic performance output voltage settling time 8 s typ full-scale step (20 v) to 0.03 % fsr 10 s max 5 s max 512 lsb step settling (@ 16 bits) slew rate 4.5 v/s typ digital-to-analog glitch energy 35 nv-sec typ glitch impulse peak amplitude 25 mv typ digital crosstalk 10 nv-sec typ dac-to-dac crosstalk 10 nv-sec typ digital feedthrough 0.1 nv-sec typ output noise (0.1 hz to 10 hz bandwidth) 0.05 lsb p-p typ output noise (100 khz bandwidth) 80 v rms max 1/f corner frequency 1 khz typ output noise spectral density 120 nv/hz typ measured at 10 khz 1 for specified perfor mance minimum headroom requirement is 0.9v 2 guaranteed by design and characterization, not production tested.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 8 of 32 timing characteristics av dd = 4.5 v to 16.5 v, av ss = ?4.5 v to ?16.5 v / 0v, gnd = 0 v, refin = 2.5 v external, dv cc = 2.7 v to 5.5 v r load = 2 k?, c load = 200 pf; all specifications t min to t max , unless otherwise noted. table 5. parameter 1, 2, 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 13 ns min sclk falling edge to sync rising edge t 6 100 ns min minimum sync high time (write mode) t 7 5 ns min data setup time t 8 0 ns min data hold time t 9 20 ns min ldac falling edge to sync falling edge t 10 20 ns min sync rising edge to ldac falling edge t 11 20 ns min ldac pulse width low t 12 1.5 s min ldac falling edge to dac output response time t 13 10 s max dac output settling time t 14 1.5 s max sync rising edge to output response time (ldac = 0) t 15 20 ns min clr pulse width low t 16 2.5 s max clr pulse activation time t 17 4 13 ns min sync rising edge to sclk rising edge t 18 4 40 ns max sclk rising edge to sdo valid (c l sdo 5 = 15 pf) t 19 200 ns min minimum sync high time (readback/daisy-chain mode) 1 guaranteed by characterization. not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 daisy-chain and readback mode. 5 c l sdo = capacitive load on sdo output.
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 9 of 32 db23 sclk sync sdin ldac clr v out x v out x v out x 12 24 db0 t 13 t 14 t 13 t 12 t 10 t 11 t 16 t 15 t 9 t 8 t 7 t 4 t 6 t 3 t 2 t 1 t 5 figure 2. serial interface timing diagram t 4 t 18 t 8 t 7 t 11 t 10 t 3 t 2 t 5 t 1 t 19 t 17 ldac sdo sdin s ync sclk 24 48 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n ? 1 input word for dac n db0 06466-003 figure 3. daisy chain timing diagram
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 10 of 32 sdo sdin sync sclk 24 24 db23 db0 db23 db0 selected register data clocked out undefined nop condition input word specifies register to be read 1 1 db23 db0 db23 db0 t 19 06466-004 figure 4. readback timing diagram
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 11 of 32 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 6. parameter rating av dd to gnd ?0.3 v to +17 v av ss to gnd +0.3 v to ?17 v dv cc to gnd ?0.3 v to +7 v digital inputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) refin/refout to gnd ?0.3 v to +17 v v out a, v out b to gnd av ss to av dd dac_gnd to gnd -0.3v to +0.3v sig_gnd to gnd -0.3v to +0.3v operating temperature range, t a industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature, t j max 105c 24-lead tssop package ja thermal impedance 90c/w power dissipation (t j max C t a )/ ja lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 12 of 32 pin configuration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad5722r/ ad5732r/ AD5752R clr ldac av ss nc v out a nc sync nc bin/2scomp gnd sdo refin/refout sig_gnd sclk sdin nc nc = no connect av dd v out b nc sig_gnd dac_gnd dac_gnd dv cc nc top view (not to scale) 06466-005 figure 5. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 av ss negative analog supply pin. voltage ranges from C4.5 v to C16.5 v. this pin can be connected to 0 v if output ranges are unipolar. 2, 4, 6, 12, 13, 22 nc do not connect to these pins. 3 v out a analog output voltage of dac a. the output amplifier is capable of directly driving a 2 k?, 4000 pf load. 5 bin/2scomp determines the dac coding for a bipolar output range. this pin should be hardwired to either dv cc or gnd. when hardwired to dv cc , input coding is offset binary. when ha rdwired to gnd, input coding is twos complement. (for unipolar output ranges, coding is always straight binary). 7 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred on the falling edge of sclk. 8 sclk serial clock input. data is clocked in to the shift register on the falling edge of sclk. this operates at clock speeds up to 30 mhz. 9 sdin serial data input. data must be valid on the falling edge of sclk. 10 ldac load dac, logic input. this is used to update the dac registers and consequently, the analog output. when tied permanently low, the addressed dac regist er is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is update d, but the output update is held off until the falling edge of ldac . in this mode, all analog outp uts can be updated simultaneously on the falling edge of ldac . the ldac pin should not be left unconnected. 11 clr 1 active low input. asserting this pin se ts the dac registers to zero-scale code or mid-scale code (user-selectable). 14 dv cc digital supply pin. voltage ranges from 2.7 v to 5.5 v. 15 gnd ground reference pin. 16 sdo serial data output. used to clock da ta from the serial register in dais y-chain or readback mode. data is clocked out on the rising edge of sclk an d is valid on the falling edge of sclk. 17 refin/refout external reference voltage input and internal reference voltage output. reference input range is 2 v to 3 v. refin = 2.5 v for specified performance. refout = 2.5 v 2 mv. 18, 19 dac_gnd ground reference pins for the four digital-to-analog converters. 20, 21 sig_gnd ground reference pins for the four output amplifiers. 23 v out b analog output voltage of dac b. the output amplifier is capable of directly driving a 2 k?, 4000 pf load. 24 av dd positive analog supply pin. voltage ranges from 4.5 v to 16.5 v. exposed paddle av ss negative analog supply connection. voltage ranges from -4.5v to -16.5v. this paddle can be connected to 0v if output ranges are unipolar. 1 internal pull-up device on this logic input. therefore, it can be left floating and defaults to a logic high.
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 13 of 32 typical performance characteristics figure 6. AD5752R integral nonlinearity error vs. code (four traces) figure 7. ad5732r integral nonlinearity error vs. code (four traces) figure 8. ad5722r integral nonlinearity error vs. code (four traces) figure 9. AD5752R differential nonlinearity error vs. code (four traces) figure 10. ad5732r differential nonlinearity error vs. code (four traces) figure 11. ad5722r differential nonlinearity error vs. code (four traces)
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 14 of 32 figure 12. AD5752R integral nonlinearity error vs. temperature (four traces) figure 13. AD5752R differential nonlineari ty error vs. temperature (four traces) figure 14. AD5752R integral nonlinearity error vs. supply voltage (four traces) figure 15. AD5752R differential nonlinearity error vs. supply voltage (four traces) figure 16. AD5752R integral nonlinearity error vs. reference voltage (four traces) figure 17. AD5752R differential nonlinearity vs. reference voltage (four traces)
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 15 of 32 figure 18. AD5752R total unadjusted error vs. reference voltage (four traces) figure 19. AD5752R total unadjusted e rror vs. supply voltage (four traces) figure 20. ai dd /ai ss vs. av dd /av ss figure 21. ai dd vs. av dd figure 22. zero-scale error vs. temperature (four traces) figure 23. bipolar zero error vs. temperature (two traces)
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 16 of 32 figure 24. gain error vs. temperature (four traces) figure 25. di cc vs. logic input voltage increasing and decreasing figure 26. output amplifier source and sink capability (four traces) figure 27. full-scale settling time, 10 v range (two traces) figure 28. full-scale settling time, 5 v range (two traces) figure 29. full-scale settling time, +10 v range (two traces)
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 17 of 32 figure 30. full-scale settling time, +5 v range (two traces) figure 31. digital-to-analog glitch energy (four traces) figure 32. peak-to-peak noise, 0.1 hz to 10 hz bandwidth (four traces) figure 33. peak-to-peak noise, 100 khz bandwidth (four traces) figure 34. v out vs. av dd /av ss on power up (two traces) figure 35. refout turn-on transient
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 18 of 32 figure 36. refout output no ise (100 khz bandwidth) figure 37. refout output noise (0 .1 hz to 10 hz bandwidth) figure 38. refout line transient (two traces) figure 39. refout load transient (two traces) figure 40. refout histogra m of thermal hysteresis figure 41. refout volt age vs. load current
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 19 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 6. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 9. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5722r/ ad5732r/AD5752R are monotonic over their full operating temperature range. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). a plot of bipolar zero error vs. temperature can be seen in figure 23. bipolar zero tc bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. zero-scale error/negative full-scale error zero-scale error is the error in the dac output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the dac register. ideally, the output voltage should be negative full-scale ? 1 lsb. a plot of zero-scale error vs. temperature can be seen in figure 22. zero-scale tc this is a measure of the change in zero-scale error with a change in temperature. zero-scale tc is expressed in ppm fsr/c. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. a plot of full-scale settling time can be seen in figure 27. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage output d/a converter is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed in % fsr. a plot of gain error vs. temperature can be seen in figure 24. gain tc this is a measure of the change in gain error with changes in temperature. gain tc is expressed in ppm fsr/c. tot a l un a dju s te d e r ror ( t u e ) total unadjusted error is a measure of the output error taking all the various errors into account, namely inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed in % fsr. power-on glitch energy power-on glitch energy is the impulse injected into the analog output when the ad5722r/ad5732r/AD5752R power on. it is normally specified as the area of the glitch in nv-sec. see figure 34. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state, but the output voltage remains constant. it is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31. glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 20 of 32 dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in lsbs. digital crosstalk digital crosstalk is a measure of the impulse injected into the analog output of one dac from the digital inputs of another dac, but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change(all 1s to all 0s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nv-sec. volt age reference tc reference tc is a measure of the change in the reference output voltage with a change in temperature. it is expressed in ppm/c.
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 21 of 32 theory of operation the ad5722r/ad5732r/AD5752R are dual, 12-/14-/16-bit, serial input, unipolar/bipolar, voltage output dacs. they operate from unipolar supply voltages of +4.5 v to +16.5 v or bipolar supply voltages of 4.5 v to 16.5 v. in addition, the parts have software-selectable output ranges of +5 v, +10 v, +10.8 v, 5 v, 10 v, and 10.8 v. data is written to the ad5722r/ad5732r/AD5752R in a 24-bit word format via a 3-wire serial interface. the devices also offer an sdo pin to facilitate daisy chaining or readback. the ad5722r/ad5732r/AD5752R incorporate a power-on reset circuit to ensure that the dac registers power up loaded with 0x0000. when powered on, the outputs are clamped to 0 v via a low impedance path. the parts also feature on-chip reference and reference buffers. architecture the dac architecture consists of a string dac followed by an output amplifier. figure 42 shows a block diagram of the dac architecture. the reference input is buffered before being applied to the dac. gnd resistor string ref (+) ref (?) configurable output amplifier output range control 06466-006 refin dac register v out x figure 42. dac architecture block diagram the resistor string structure is shown in figure 43. it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to outpu t amplifier refin 06466-007 figure 43. resistor string structure output amplifiers the output amplifiers are capable of generating both unipolar and bipolar output voltages. they are capable of driving a load of 2 k? in parallel with 4000 pf to gnd. the source and sink capabilities of the output amplifiers can be seen in figure 26. the slew rate is 4.5 v/s with a full-scale settling time of 10 s. reference buffers the ad5722r/ad5732r/AD5752R can operate with either an external or internal reference. the reference input has an input range of 2 v to 3 v with 2.5 v for specified performance. this input voltage is then buffered before it is applied to the dac cores. serial interface the ad5722r/ad5732r/AD5752R are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 mhz. it is compatible with spi?, qspi?, microwire?, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk. the input register consists of a read/write bit, three register select bits, three dac address bits, and 16 data bits. the timing diagram for this operation is shown in figure 2.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 22 of 32 standalone operation the serial interface works with both a continuous and noncon- tinuous serial clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. when the data has been transferred into the chosen register of the addressed dac, all dac registers and outputs can be updated by taking ldac low while sync is high. * additional pins omitted for clarity. 68hc11 * miso sdin sclk mosi sck pc7 pc6 sdo sclk sdo sclk sdo sdin sdin sync sync sync ldac ldac ldac ad5722r/ ad5732r/ AD5752R* ad5722r/ ad5732r/ AD5752R* ad5722r/ ad5732r/ AD5752R* 06466-008 figure 44. daisy chaining the ad5722r/ad5732r/AD5752R daisy-chain operation for systems that contain several devices, the sdo pin can be used to daisy chain several devices together. daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n , where n is the total number of ad5722r/ad5732r/AD5752R devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be a continuous or a gated clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. readback operation readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. (if the sdo output is disabled via the sdo disable bit in the control register, it is automatically enabled for the duration of the read operation after which it is disabled again). with r/ w = 1, bit a2 to bit a0 in association with bit reg2 to bit reg0 select the register to be read. the remaining data bits in the write sequence are dont care bits. during the next spi write, the data appearing on the sdo output contains the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in figure 4 shows the readback sequence. for example, to read back the data register of channel a, the following sequence should be implemented: 1. write 0x800000 to the ad5722r/ad5732r/AD5752R input register. this configures the part for read mode with the data register of channel a selected. note that all the data bits, db15 to db0, are dont care bits. 2. follow this with a second write, a nop condition, 0x180000. during this write, the data from the register is clocked out on the sdo line.
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 23 of 32 load dac (ldac ) after data has been transferred into the input register of the dacs, there are two ways to update the dac registers and dac outputs. depending on the status of both sync and ldac , one of two update modes is selected, individual dac updating or simultaneous updating of all dacs. sync sclk v out dac register interface logic output amplifier ldac sdo sdin v refin input register 12-/14-/16-bit dac 06466-009 figure 45. simplified diagram of input loading circuitry for one dac individual dac updating in this mode, ldac is held low while data is being clocked into the input shift register. the addressed dac output is updated on the rising edge of sync . simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the input shift register. all dac outputs are asynchronously updated by taking ldac low after sync has been taken high. the update now occurs on the falling edge of ldac . asynchronous clear (clr ) clr is an active low clear that allows the outputs to be cleared to either zero-scale code or mid-scale code. the clear code value is user-selectable via the clr select bit of the control register (see the control register section). it is necessary to maintain clr low for a minimum amount of time to complete the operation (see figure 2). when the clr signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the clr pin is low. a clear operation can also be performed via the clear command in the control register. configuring the ad5 722r/ad5732r/AD5752R when the power supplies are applied to the ad5722r/ad5732r/ AD5752R, the power-on reset circuit ensures that all registers default to 0. this places all channels and the internal reference in power-down mode. the first communication to the ad5722r/ad5732r/AD5752R should be to set the required output range on all channels (default range is the 5 v unipolar range) by writing to the range select register. the user should then write to the power-control register to power-on the required channels and the internal reference, if required. if an external reference source is being used, the internal reference must remain in power-down mode. to program an output value on a channel, that channel must first be powered up; any writes to a channel while it is in power-down mode are ignored. the ad5722r/ad5732r/AD5752R operate with a wide power supply range. it is important that the power supply applied to the parts provides adequate headroom to support the chosen output ranges. transfer function table 9 to table 17 show the relationships of the ideal input code to output voltage for the AD5752R, ad5732r, and ad5722r, respectively, for all output voltage ranges. for unipolar output ranges, the data coding is straight binary. for bipolar output ranges, the data coding is user-selectable via the bin/ 2scomp pin and can be either offset binary or twos complement. for a unipolar output range, the output voltage expression is given by ? ? ? ? ? ? = 2 for a bipolar output range, the output voltage expression is given by 2 2 refin n refin out v gain d gain v v ? ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac. v refin is the reference voltage applied at the refin pin. gain is an internal gain whose value depends on the output range selected by the user as shown in table 8. table 8. output range (v) gain value +5 2 +10 4 +10.8 4.32 5 4 10 8 10.8 8.64
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 24 of 32 ideal output voltage to input code relationshipAD5752R table 9. bipolar output, offset binary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 1111 1111 1111 1111 +2 refin(32767/32768) +4 refin(32767/32768) +4.32 refin(32767/32768) 1111 1111 1111 1110 +2 refin(32766/32768) +4 refin(32766/32768) +4.32 refin(32766/32768) C C C C C C C 1000 0000 0000 0001 +2 refin(1/32768) +4 refin(1/32768) +4.32 refin(1/32768) 1000 0000 0000 0000 0 v 0 v 0 v 0111 1111 1111 1111 ?2 refin(1/32768) ?4 refin(1/32768) ?4.32 refin(32766/32768) C C C C C C C 0000 0000 0000 0001 ?2 refin(32766/32768) ?4 refin(32766/32768) ?4.32 refin(32766/32768) 0000 0000 0000 0000 ?2 refin(32767/32768 ?4 refin(32767/32768) ?4.32 refin(32767/32768) table 10. bipolar output, twos complement coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 0111 1111 1111 1111 +2 refin(32767/32768) +4 refin(32767/32768) +4.32 refin(32767/32768) 0111 1111 1111 1110 +2 refin(32766/32768) +4 refin(32766/32768) +4.32 refin(32766/32768) C C C C C C C 0000 0000 0000 0001 +2 refin(1/32768) +4 refin(1/32768) +4.32 refin(1/32768) 0000 0000 0000 0000 0 v 0 v 0 v 1111 1111 1111 1111 ?2 refin(1/32768) ?4 refin(1/32768) ?4.32 refin(1/32768) C C C C C C C 1000 0000 0000 0001 ?2 refin(32766/32768) ?4 refin(32766/32768) ?4.32 refin(32766/32768) 1000 0000 0000 0000 ?2 refin(32767/32768) ?4 refin(32767/32768) ?4.32 refin(32767/32768) table 11. unipolar output, straight binary coding digital input analog input msb lsb +5 v output range +10 v output range +10.8 v output range 1111 1111 1111 1111 +2 refin(65535/65536) +4 refin(65535/65536) +4.32 refin(65535/65536) 1111 1111 1111 1110 +2 refin(65534/65536) +4 refin(65534/65536) +4.32 refin(65534/65536) C C C C C C C 1000 0000 0000 0001 +2 refin(32769/65536) +4 refin(32769/65536) +4.32 refin(32769/65536) 1000 0000 0000 0000 +2 refin(32768/65536) +4 refin(32768/65536) +4.32 refin(32768/65536) 0111 1111 1111 1111 +2 refin(32767/65536) +4 refin(32767/65536) +4.32 refin(32767/65536) C C C C C C C 0000 0000 0000 0001 +2 refin(1/65536) +4 refin(1/65536) +4.32 refin(1/65536) 0000 0000 0000 0000 0 v 0 v 0 v
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 25 of 32 ideal output voltage to input code relationshipad5732r table 12. bipolar output, offset binary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 11 1111 1111 1111 +2 refin(8191/8192) +4 refin(8191/8192) +4.32 refin(8191/8192) 11 1111 1111 1110 +2 refin(8190/8192) +4 refin(8190/8192) +4.32 refin(8190/8192) C C C C C C C 10 0000 0000 0001 +2 refin(1/8192) +4 refin(1/8192) +4 refin(1/8192) 10 0000 0000 0000 0 v 0 v 0 v 01 1111 1111 1111 ?2 refin(1/8192) ?4 refin(1/8192) ?4.32 refin(1/8192) C C C C C C C 00 0000 0000 0001 ?2 refin(8190/8192) ?4 refin(8190/8192) ?4.32 refin(8190/8192) 00 0000 0000 0000 ?2 refin(8191/8191) ?4 refin(8191/8192) ?4.32 refin(8191/8192) table 13. bipolar output, twos complement coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 01 1111 1111 1111 +2 refin(8191/8192) +4 refin(8191/8192) +4.32 refin(8191/8192) 01 1111 1111 1110 +2 refin(8190/8192) +4 refin(8190/8192) +4.32 refin(8190/8192) C C C C C C C 00 0000 0000 0001 +2 refin(1/8192) +4 refin(1/8192) +4 refin(1/8192) 00 0000 0000 0000 0 v 0 v 0 v 11 1111 1111 1111 ?2 refin(1/8192) ?4 refin(1/8192) ?4.32 refin(1/8192) C C C C C C C 10 0000 0000 0001 ?2 refin(8190/8192) ?4 refin(8190/8192) ?4.32 refin(8190/8192) 10 0000 0000 0000 ?2 refin(8191/8192) ?4 refin(8191/8192) ?4.32 refin(8191/8192) table 14. unipolar output, straight binary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 11 1111 1111 1111 +2 refin(16383/16384) +4 refin(16383/16384) +4.32 refin(16383/16384) 11 1111 1111 1110 +2 refin(16382/16384) +4 refin(16382/16384) +4.32 refin(16382/16384) C C C C C C C 10 0000 0000 0001 +2 refin(8193/16384) +4 refin(8193/16384) +4.32 refin(8193/16384) 10 0000 0000 0000 +2 refin(8192/16384) +4 refin(8192/16384) +4.32 refin(8192/16384) 01 1111 1111 1111 +2 refin(8191/16384) +4 refin(8191/16384) +4.32 refin(8191/16384) C C C C C C C 00 0000 0000 0001 +2 refin(1/16384) +4 refin(1/16384) +4.32 refin(1/16384) 00 0000 0000 0000 0 v 0 v 0 v
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 26 of 32 ideal output voltage to input code relationshipad5722r table 15. bipolar output, offset binary coding digital input analog output msb lsb 5 v output range 10 v output range 10.8 v output range 1111 1111 1111 +2 refin(2047/2048) +4 refin(2047/2048) +4.32 refin(2047/2048) 1111 1111 1110 +2 refin(2046/2048) +4 refin(2046/2048) +4.32 refin(2046/2048) C C C C C C 1000 0000 0001 +2 refin(1/2048) +4 refin(1/2048) +4 refin(1/2048) 1000 0000 0000 0 v 0 v 0 v 0111 1111 1111 ?2 refin(1/2048) ?4 refin(1/2048) ?4.32 refin(1/2048) C C C C C C 0000 0000 0001 ?2 refin(2046/2048) ?4 refin(2046/2048) ?4.32 refin(2046/2048) 0000 0000 0000 ?2 refin(2047/2047) ?4 refin(2047/2048) ?4.32 refin(2047/2048) table 16. bipolar output, twos complement coding digital output analog output msb lsb 5 v output range 10 v output range 10.8 v output range 0111 1111 1111 +2 refin(2047/2048) +4 refin(2047/2048) +4.32 refin(2047/2048) 0111 1111 1110 +2 refin(2046/2048) +4 refin(2046/2048) +4.32 refin(2046/2048) C C C C C C 0000 0000 0001 +2 refin(1/2048) +4 refin(1/2048) +4 refin(1/2048) 0000 0000 0000 0 v 0 v 0 v 1111 1111 1111 ?2 refin(1/2048) ?4 refin(1/2048) ?4.32 refin(1/2048) C C C C C C 1000 0000 0001 ?2 refin(2046/2048) ?4 refin(2046/2048) ?4.32 refin(2046/2048) 1000 0000 0000 ?2 refin(2047/2048) ?4 refin(2047/2048) ?4.32 refin(2047/2048) table 17. unipolar output, straight binary coding digital input analog output msb lsb +5 v output range +10 v output range +10.8 v output range 1111 1111 1111 +2 refin(4095/4096) +4 refin(4095/4096) +4.32 refin(4095/4096) 1111 1111 1110 +2 refin(4094/4096) +4 refin(4094/4096) +4.32 refin(4094/4096) C C C C C C 1000 0000 0001 +2 refin(2049/4096) +4 refin(2049/4096) +4.32 refin(2049/4096) 1000 0000 0000 +2 refin(2048/4096) +4 refin(2048/4096) +4.32 refin(2048/4096) 0111 1111 1111 +2 refin(2047/4096) +4 refin(2047/4096) +4.32 refin(2047/4096) C C C C C C 0000 0000 0001 +2 refin(1/4096) +4 refin(1/4096) 4.32 refin(1/4096) 0000 0000 0000 0 v 0 v 0 v
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 27 of 32 input register the input register is 24 bits wide and consists of a read/write bit, a reserved bit, three register select bits, three dac addr ess bits, and 12- /14-/16 data bits. the register data is clocked in msb first on the sdin pin. table 18 shows the register format while table 19 describes the function of each bit in the register. all registers are read/write registers. table 18. input register format msb lsb db23 db22 db21 db20 db19 db 18 db17 db16 db15 to db0 r/ w 0 reg2 reg1 reg0 a2 a1 a0 data table 19. input register bit functions bit mnemonic description r/w indicates a read from or a write to the addressed register. reg2, reg1, reg0 used in association with the address bits to determine if a write operation is to the data register, output range select register, power control register, or control register. reg2 reg1 reg0 function 0 0 0 data register 0 0 1 output range select register 0 1 0 power control register 0 1 1 control register a2, a1, a0 these bits are used to decode the dac channels. a2 a1 a0 channel address 0 0 0 dac a 0 1 0 dac b 1 0 0 both dacs db15 to db0 data bits. data register the data register is addressed by setting the three reg bits to 000. the dac address bits select the dac channel where the data transfer is to take place (see table 19). the data bits are in positions db15 to db0 for the AD5752R (see table 20), db15 to db2 for the ad5732r (see table 21), and db15 to db4 for the ad5722r (see table 22). table 20. programming the AD5752R data register msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db0 0 0 0 dac address 16-bit dac data table 21. programming the ad5732r data register msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db2 db1 db0 0 0 0 dac address 14-bit dac data x x table 22. programming the ad5722r data register msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 0 0 dac address 12-bit dac data x x x x
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 28 of 32 output range select register the output range select register is addressed by setting the three reg bits to 001. the dac address bits select the dac channel , while, the range bits (r2, r1, r0) select the required output range (see table 23 and table 24). table 23. programming the required output range msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db3 db2 db1 db0 0 0 0 dac address dont care r2 r1 r0 table 24. output range options r2 r1 r0 output range (v) 0 0 0 +5 0 0 1 +10 0 1 0 +10.8 0 1 1 5 1 0 0 10 1 0 1 10.8 control register the control register is addressed by setting the three reg bits to 011. the value written to the address and data bits determin es the control function selected. the control register options are shown in table 25 and table 26. table 25. control register format msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 1 1 0 0 0 nop, data = dont care reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 1 1 0 0 1 dont care tsd enable clamp enable clr select sdo disable reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 1 1 1 0 0 clear, data = dont care reg2 reg1 reg0 a2 a1 a0 db15 to db4 db3 db2 db1 db0 0 1 1 1 0 1 load, data = dont care table 26. explanation of control register options option description nop no operation instruction used in readback operations. clear addressing this function sets the dac regi sters to the clear code and updates the outputs. load addressing this function updates the da c registers and consequently, the dac outputs. sdo disable set by the user to disabl e the sdo output. cleared by the user to enable the sdo output (default). clr select see table 27 for a description of the clr select operation. clamp enable set by the user to enable the current limit clamp. the channel does not power down on detection of overcurrent; the current is clamped at 20 ma (default). cleared by the user to enable the current-limit clamp. the channel powers down on detection of overcurrent. tsd enable set by the user to enable the therma l shutdown feature. cleared by the us er to disable the thermal shutdown feature (default). table 27. clr select options clr select output clr value setting unipolar output range bipolar output range 0 0 v 0 v 1 mid-scale negative full-scale
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 29 of 32 power control register the power control register is addressed by setting the three reg bits to 010. this register allows the user to control and dete rmine the power and thermal status of the ad5722r/ad5732r/AD5752R. the power control register options are shown in table 28 and table 29. table 28. power control register format msb lsb reg2 reg1 reg0 a2 a1 a0 db15 to db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 0 dont care x oc b x oc a 0 tsd pu ref x pu b x pu a table 29. explanation of status register options option description pu a dac a power-up. when set, this bit places dac a in normal opera ting mode. when cleared, this bit places dac a in power-down mode (default). if the clamp enable bit of the control register is cleared, dac a will power down autimatically on detection of an over-current, pu a will be cleared to reflect this. pu b dac b power-up. when set, this bit places dac b in normal oper ating mode. when cleared, this bit places dac b in power-down mode (default). if the clamp enable bit of the control register is cleared, dac b will power down autimatically on detection of an over-current, pu b will be cleared to reflect this. pu ref reference power-up. when set, this bit places the internal refere nce in normal operating mode. when cleared, this bit places th e internal reference in power-down mode (default). tsd thermal shutdown alert. read-only bit. in the even t of an overtemperature situation, this bit is set. oc a dac a overcurrent alert. read-only bit. in the event of an overcurrent situation on dac a, this bit is set. oc b dac b overcurrent alert. read-only bit. in the event of an overcurrent situation on dac b, this bit is set.
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 30 of 32 features analog output control in many industrial process control applications, it is vital that the output voltage be controlled during power-up. when the supply voltages change during power-up, the v out pins are clamped to 0 v via a low impedance path (approxiamately 4k ? ). to prevent the output amplifiers from being shorted to 0 v during this time, transmission gate g1 is also opened (see figure 46). these conditions are maintained until the power supplies have stabilized and a valid word is written to a dac register. at this time, g2 opens and g1 closes. v out a g1 g2 voltage monitor and control 0 6466-010 figure 46. analog output control circuitry overcurrent protection each dac channel of the ad5722r/ad5732r/AD5752R incorporates individual overcurrent protection. the user has two options for the configuration of the overcurrent protection, constant current clamp or automatic channel power-down. the configuration of the overcurrent protection is selected via the clamp enable bit in the control register. constant current clamp (clamp enable = 1) if a short circuit occurs in this configuration, the current is clamped at 20 ma. this event is signaled to the user by the setting of the appropriate overcurrent (oc x ) bit in the power control register. upon removal of the short-circuit fault, the oc x bit is cleared. automatic channel power-down (clamp enable =0) if a short circuit occurs in this configuration, the shorted channel powers down, and its output is clamped to ground via a resistance of approxiamately 4k ? , also at this time the output of the amplifier is disconnected from the output pin. the short- circuit event is signaled to the user via the overcurrent (oc x ) bits, while the power-up (pu x ) bits indicate which channels have powered down. after the fault is rectified, the channels can be powered up again by setting the pu x bits. thermal shutdown the ad5722r/ad5732r/AD5752R incorporate a thermal shutdown feature that automatically shuts down the device if the core temperature exceeds approximately 150c. the thermal shutdown feature is disabled by default and can be enabled via the tsd enable bit of the control register. in the event of a thermal shutdown, the tsd bit of the power control register is set. internal reference the on-chip voltage reference is powered down by default. if an external voltage reference source is to be used, the internal reference must remain powered down at all times. if the internal reference is to be used as the reference source, it must be powered up via the pu ref bit of the power control register. the internal reference voltage is accessible at the refin/refout pin for use as a reference source for other devices within the system. if the internal reference is to be used external to the ad5722r/ad5732r/AD5752R, it must first be buffered.
preliminary technical data ad5722r/ad5732r/AD5752R rev. prc | page 31 of 32 applications information +5v / 5v operation when operating from a single +5v supply or a dual 5v supply an output range of +5v or 5v is not achievable as sufficient headroom for the output amplifier is not available. in this situation a reduced reference voltage can be used, for instance a 2v reference voltage will produce an output range of +4v or 4v, the 1v of headroom is more than rnough for full operation. a standard value voltage reference of 2.048v can be used to produce output ranges of +4.096v and 4.096v. refer to the typical performance characteristics plots for performance data at a range of voltage reference values. layout guidelines in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5722r/ad5732r/AD5752R are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5722r/ ad5732r/AD5752R are in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5722r/ad5732r/AD5752R should have an ample supply bypassing of a 10 f capacitor in parallel with a 0.1 f capacitor on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5722r/ad5732r/AD5752R should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines does help). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. the i coupler? family of products from analog devices provides voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5722r/ad5732r/AD5752R make them ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 47 shows a 4-channel isolated interface to the ad5722r/ad5732r/AD5752R using an adum1400 . for further information, visit http://www.analog.com/icouplers. encode decode encode decode encode decode v ia v ib v ic v id v oa v ob v oc v od encode decode a dum1 4 00* microcontroller serial clock out serial data out sync out control out to sclk to sdin to sync to ldac *additional pins omitted for clarity. 06466-011 figure 47. isolated interface microprocessor interfacing microprocessor interfacing to the ad5722r/ad5732r/AD5752R is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5722r/ad5732r/AD5752R require a 24-bit data-word with data valid on the falling edge of sclk. for all interfaces, the dac output update can be initiated automatically when all the data is clocked in, or it can be performed under the control of ldac . the contents of the registers can be read using the readback function. ad5722r/ad5732r/AD5752R to blackfin ? dsp interface figure 48 shows how the ad5722r/ad5732r/AD5752R can be interfaced to analog devices blackfin dsp. the blackfin has an integrated spi port that can be connected directly to the spi pins of the ad5722r/ad5732r/AD5752R and the programmable i/o pins that can be used to set the state of a digital input such as the ldac pin. sync adsp-bf531 ad5722r/ ad5732r/ AD5752R sclk sdin spiselx sck mosi ldac pf10 06466-012 figure 48. ad5722r/ad5732r/AD5752R to blackfin interface
ad5722r/ad5732r/AD5752R preliminary technical data rev. prc | page 32 of 32 outline dimensions compliant to jedec standards mo-153-adt 050806-a 24 13 12 1 6.40 bsc 0.15 0.05 0.10 coplanarity top view exposed pad (pins up) bottom view 4.50 4.40 4.30 7.90 7.80 7.70 1.20 max 1.05 1.00 0.80 0.65 bsc 0.30 0.19 seating plane 0.20 0.09 8 0 0.75 0.60 0.45 5.02 5.00 4.95 3.25 3.20 3.15 figure 49. 24-lead thin shrink small ou tline package, exposed pad [tssop_ep] (re-24) dimensions shown in millimeters ordering guide model resolution temperature range inl package description package option ad5722rbrez 1 12 ?40c to 85c 1 lsb 24-lead tssop_ep re-24 ad5722rbrez-reel7 1 12 ?40c to 85c 1 lsb 24-lead tssop_ep re-24 ad5732rbrez 1 14 ?40c to 85c 4 lsb 24-lead tssop_ep re-24 ad5732rbrez-reel7 1 14 ?40c to 85c 4 lsb 24-lead tssop_ep re-24 AD5752Rbrez 1 16 ?40c to 85c 16 lsb 24-lead tssop_ep re-24 AD5752Rbrez-reel7 1 16 ?40c to 85c 16 lsb 24-lead tssop_ep re-24 1 z = pb-free part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06466-0-11/07(prc)

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